(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to the formation of copper interconnective metallization.
(2) Background of the Invention and Description of Related Art
Integrated circuits are manufactured by forming discrete semiconductor devices in the surface of silicon wafers. A multi-level metallurgical interconnection network is then formed over the devices, contacting their active elements, and wiring them together to create the desired circuits. The wiring layers are formed by depositing an insulating layer over the discrete devices, patterning and etching contact openings into this layer, and then depositing conductive material into the openings. A conductive layer is applied over the insulating layer and patterned to form wiring interconnections between the device contacts, thereby creating a first level of basic circuitry. The circuits are then further interconnected by utilizing additional wiring levels laid out over additional insulating layers with conductive via pass throughs. Depending upon the complexity of the overall integrated circuit, several levels of wiring interconnections are used.
For many years, aluminum and aluminum alloys were the most widely used interconnection metallurgies for integrated circuits. Copper had previously been contemplated for replacing aluminum because of it""s higher conductivity which results in improved circuit performance. However, a copper metallurgy faced two major problems. Firstly, deposited copper films are difficult to etch in order to form wiring patterns and secondly copper is known to diffuse rapidly in silicon causing junction failure, often referred to as junction poisoning. Copper can also diffuse through insulative layers, degrading them, as well as eventually traveling though them and into device regions.
The problem of forming copper wiring patterns has now been successfully overcome by using a damascene process, whereby openings and trenches, comprising an image of an interconnection pattern, are formed in an insulative layer. Copper is deposited into these openings and over the insulative layer and polished back to the insulative layer leaving a copper wiring pattern, inlaid within the insulative layer. Polishing back of the metal layer is accomplished by CMP (chemical mechanical polishing), a relatively old process which has found new application and refinement in planarization of insulative layers and, more recently, in the damascene process. In a single damascene process a metal line pattern is generated which connects to subjacent vias or contacts. In a dual damascene process, both vias/contacts and an interconnective wiring pattern are formed by a single metal deposition and CMP. A description of both single and dual damascene processes may be found in Chang, C. Y. and Sze, S. M., xe2x80x9cULSI Technologyxe2x80x9d McGraw-Hill, New York, (1996), p444-445 and in El-Kareh, B., xe2x80x9cFundamentals of Semiconductor Processing Technologiesxe2x80x9d, Kluwer, Boston(1995), p563-4.
The dual damascene process has been particularly favored for the manufacture of integrated circuits using copper metallurgy. Copper is rapidly replacing aluminum as the metallurgy of choice in integrated circuit manufacturing because it has a higher conductivity than aluminum. The use of copper results in greatly improved circuit performance.
The problem of copper migration into the silicon and diffusing into dielectric layers has been overcome by applying a copper diffusion barrier between the copper and the dielectric layers as well as between the copper and the silicon substrate. A variety of effective barrier materials have been reported. These materials, include conductive compounds of transition metals such as tantalum nitride, titanium nitride, and tungsten nitride as well as the various transition metals themselves. Insulators such as silicon nitride, silicon oxynitride and PSG (a phophosilicate glass) are also effective barrier materials between copper metallurgy and insulative layers. Nogami, et. al., U.S. Pat. No. 6,001,415 cites a number of materials, including Ta and TaN, which are effective against copper diffusion. Liu, et. al., U.S. Pat. No. 6,010,962 cites a damascene process wherein Ta is used as a barrier layer.
In order to further improve circuit performance, low dielectric constant (low-k) materials have been incorporated into the dielectric layers of modern integrated circuits. These materials provide a lower capacitance than conventional silicon oxide and consequently, an increase in circuit speed. Examples of low-k dielectric materials include the SOGs (spin-on-glasses). SOGs are formed from alcohol soluble siloxanes or silicates which are spin deposited and baked to form a relatively porous silicon oxide structure. Other porous silica structures such as xerogels have been developed, notably by Texas Instruments Inc. and incorporated into dual damascene processes to obtain dielectric layers with dielectric constants as low as 1.3. This is to be compared with a dielectric constant of about 4 for conventional silicon oxide.
Organic and quasi-organic materials such as polysilsesquioxanes, FSG (fluorinated silica glass) and fluorinated polyarylene ethers have been added to the growing family of low-k and ultra low-k dielectric materials. The totally organic, non silicaceous, materials such as the fluorinated polyarylene ethers, are seeing an increased usage in semiconductor processing technology because of their favorable dielectric characteristics and ease of application. Organosilicate glasses (OSGs), for example Black Diamond(trademark), from Applied Materials Corporation of Santa Clara Calif., have dielectric constants as low as 2.6-2.8. These are low density silicate glasses to which alkyl groups have been added to achieve a low-k.
Farkas, et. al., U.S. Pat. No. 6,001,730 shows a damascene structure with a tantalum based barrier layer on low-k dielectric materials. While Ta is an effective copper barrier, it is difficult to remove over the planar regions by the copper CMP process. TaN is also a more effective as a copper barrier than Ta.
It is found, however, that TaN barrier films deposited directly onto certain low-k dielectric materials, in particular, fluorinated low-k materials such as FSGs and OSGs such as Black Diamond, exhibit poor adhesion. This results in catastrophic delamination of the barrier material, either immediately after deposition or during subsequent processing. De-lamination is produced by high tensile stresses as well as weak bonding between TaN barrier layers and low-k dielectric layers. While Farkas does not admit to barrier adhesion problems with low-k materials, it is known that barrier adhesion to low-k is a serious problem in the industry. Venkatraman, et. al., U.S. Pat. No. 5,814,557 shows a barrier layer for a copper dual damascene process but the layer is not applied onto low-k dielectric layers and therefore barrier adhesion problems are not at issue.
It is therefore desirable to have a method for improving the adhesion of a TaN copper diffusion barrier to low-k dielectric layers. The present invention provides a method which not only greatly improves the adhesion of a TaN barrier layer on a low-k dielectric layer but also improves the interface between the TaN barrier layer and the copper seed layer which is deposited on top of the barrier layer.
Accordingly, it is an object of this invention to provide a method for forming a well bonded, reduced tensile stress copper barrier layer on low-k dielectric layers.
It is another object of this invention to provide a method for improving the adhesion of a TaN barrier layer on a low-k dielectric layer.
It is yet another object of this invention to provide method for preventing delamination of copper barrier layers deposited onto low-k dielectric layers during thermal processing.
It is still another object of this invention to provide method for improving the wetting capability of a copper barrier layer thereby improving the structure of copper seed layers deposited thereon.
These objects are accomplished by forming a laminar Ta/TaN/Ta barrier layer by depositing an initial Ta rich layer onto a low-k dielectric layer, thereby providing sufficient excess Ta to form a strong tensile stress free interfacial bonding layer, depositing a thicker stoichiometric TaN portion on the Ta rich layer, and finally depositing a second Ta rich layer on the TaN portion to create a Ta enriched surface. The initial Ta is layer is deposited under low Ta deposition rate conditions and in just enough amount to form a transition layer comprising a mixture of Ta and the low-k material. The final Ta rich layer provides a better wetting surface for the subsequently deposited copper seed layer thereby improving the  less than 111 greater than  texture of the seed layer. The three graded layers of the barrier are deposited sequentially in a single pumpdown operation using an IMP(ion metal plasma) sputter deposition tool. The initial and final Ta rich layers are deposited at low DC power/high substrate bias conditions, later referred to as Lo/HB, while the stoichiometric TaN middle portion is deposited under conventional power/bias deposition conditions. This allows the three layers to be properly graded into each other thereby reducing interfacial stresses within the barrier.